`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:31:33 10/15/2010 
// Design Name: 
// Module Name:    counter_10bit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module counter# ( parameter N = 10 )(
    input clk,
    input enable,
    input reset,
    output [N-1:0] out
    );

reg [N-1:0] temp;
assign out[N-1:0] = temp[N-1:0];

always@( posedge clk , posedge reset)
begin

		if( reset )
		begin
			temp <= 0;
		end
		else if ( enable)
		begin
			temp <= temp + 1;
		end
end
			

endmodule
